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| geometry process details principal device types 2n4033 cmpt4033 cxt4033 czt4033 gross die per 4 inch wafer 11,212 process cp705 small signal transistor pnp - high current transistor chip process epitaxial planar die size 31 x 31 mils die thickness 9.0 mils base bonding pad area 5.9 x 11.8 mils emitter bonding pad area 6.5 x 13.8 mils top side metalization al - 30,000? back side metalization au - 18,000? www.centralsemi.com r4 (22-march 2010)
process cp705 typical electrical characteristics www.centralsemi.com r4 (22-march 2010) |
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